By Steyaert M. (ed.), van Roermund A.H.M. (ed.), Casier H. (ed.)
Analog Circuit layout includes the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and necessary layout rules within the zone of analog circuit layout. each one half is gifted through six specialists in that box and cutting-edge info is shared and overviewed. This publication is quantity 17 during this profitable sequence of Analog Circuit layout.
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Extra resources for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
In particular the focus is on SATA, SAS and FC standards. 5 Gb/s in FC; Cable and backplane equalization is a common requirement, even if at different frequencies and channel losses; The maximum frequency difference between a FC transmitter and receiver is limited to +/– 200 ppm, while in SATA and SAS, for EMI suppression, the transmitted data can be modulated in frequency by a 30 kHz triangular shape, with a maximum amplitude of 5000 ppm (Spread Spectrum Clock – SSC); FC must assure shorter locking time (2500 bits) and serial to parallel data latency.
24 Duobinary channel and detection sampling points clock pattern is no more possible: data encoding and frequency drift requirements must be set coherently, in order to make duobinary communication feasible. Figure 25 shows the ‘eye’ seen by the top duobinary sampler: the samplers A1 and A2 in Fig. 25a would detect the same bit, thus leading to the conclusion that the effective eye is the one shown in Fig. 25b. In case the channel is not well equalized to duobinary, either because the clock is not suppressed or because low frequency channel equalization is not enough, the position of the duobinary threshold is no more optimized; anyway, an eye still exists and another optimal decision point can be found, as shown in Fig.
22 CDR implementation additional requirements come from the maximum frequency drift to be tracked, expressed by the following relation: P P Mmax = I valmax · 1e6 C A · N P H · N dmx (5) A high frequency drift capability requires either a small demuxing ratio or a low number of phase rotator phases. On the other hand, sizing the loop for a high frequency drift, as required in SATA/SAS, would limit the frequency resolution in FC, where the maximum drift is +/− 200 ppm, only. For these reasons, the CDR in Fig.